III-V compounds offer a number of advantages over silicon with respect to the operation of semiconductor devices such as field-effect transistors. The heterointegration of III-V compounds on materials such as silicon allows the co-integration of III-V nFETs with SiGe pFETs. III-V and CMOS is one possible option for sub-10 nm technology nodes.
Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). III-V FinFETs fabricated on silicon wafers offer performance advantages over devices based entirely on silicon.
The lattice mismatch between silicon and many III-V semiconductor materials needs to be addressed when combining such materials in an electronic device. Aspect ratio trapping (ART) is an effective technique to trap threading dislocations, thereby reducing the dislocation density of lattice mismatched materials grown on silicon.